1. Field of the Invention
The present invention relates generally to microprocessors and more particularly to transmission of isochronous data between a peripheral device and an MMx unit of a microprocessor.
2. Description of the Relevant Art
The continuing proliferation of computer development and applications has lead to computer systems that incorporate "multimedia" capability. That is, present computer technology allows for the processing of audio and video information as such information is generated by devices external to the central processing unit (CPU) or computer. For example, multimedia computers may present video images and/or audio tracks from a medium such as a CD-ROM.
FIG. 1 shows a typical prior art computer system depicting the elements relevant to the present discussion. A central processing unit (CPU) core 10 is coupled to an L1 cache system 15 and a bus input/output (I/O) device 16 over a CPU local bus 8. The L1 cache system 15 typically includes a cache controller and a cache SRAM (not shown). The CPU core 10, L1 cache system 15, and bus I/O 16 may be implemented as separate discrete components but preferably are integrated onto a single chip processor as indicated by dashed box 9.
The bus I/O device 16 couples the CPU local bus 8 to a memory bus 11. A memory control unit or memory controller 12 also couples to the memory bus 11. A second level cache, referred to as an L2 cache 7, couples to the memory bus 11 and also couples to the memory control unit 12. The memory control unit 12 couples to a memory device 13. The memory device 13 typically is dynamic random access memory (DRAM).
A bus bridge 17 couples the memory bus 11 to a peripheral bus 18. Peripheral devices 19 are coupled to the peripheral bus. A multimedia device 190 represents one type of peripheral device which is coupled to the peripheral bus 18. Examples of multimedia devices are CD-ROM drives, graphics cards, video recorders, sound cards, modems, and the like.
The CPU core 10 and peripheral devices 19 and 190 communicate through the bus bridge 17 in different ways. A simple communication scheme allows data from the CPU core 10 to be placed on the CPU local bus 11 and transferred through the bus I/O device 16, memory bus 11, bus bridge 17, peripheral bus 18, and to a peripheral device/multimedia device. Data communication from the peripheral devices 19 and 190 to the CPU core 10 follows the same path, albeit in the reverse order.
The CPU core 10 typically engages in multiple activities such as access cycles to the memory device 13 through memory control unit 12, accesses to the L1 cache SRAM 15, as well as receiving and transmitting data to a variety of peripheral devices 19/190. The CPU core 10 often performs digital signal processing (DSP) operations on video and audio data to and from the multimedia device 190. Digital signal processing is a time-consuming, iterative process often involving vast amounts of data and requiring a large portion of the CPU's computing resources. Multimedia data often comprises real-time, isochronous data (i.e., video and audio data metered out in regular time periods). For real-time data, such as video and audio, to be effectively observed by the human user, it must be performed (e.g., video data displayed on a monitor or sound data provided to speakers) at the same rate at which the data was acquired originally. Any delays in processing will render music or motion pictures, for example, unintelligible and useless. As such, multimedia data often requires processing by the CPU "on the fly" or "in real time."
These demands on the CPU's processing power often renders direct communication between a multimedia device 190 and the CPU core 10 impractical because the CPU generally can receive, transmit, and process data much faster than the multimedia device 190. Direct data transmission between CPU and multimedia device, consequently, may not be the most efficient transmission scheme in light of other processing demands on the CPU. Consequently, data from the multimedia device may be stored or buffered in the memory 13. Once in the memory, the CPU core 10 can retrieve the multimedia data more efficiently as larger blocks of data can be retrieved with less access overhead than with datum by datum transfers directly between multimedia device and CPU.
However, latency effects may render memory structures incapable of allowing real-time blocks of data to be stored, retrieved, and processed without detrimentally effecting the data's real-time nature. Further, latency in accessing DRAM often is unpredictable. For example, video data that is stored in the memory device 13 and periodically processed by the CPU core 10 with the latency inherent to the system may result in dropped frames or missed audio data, thereby resulting in jerky video and poor audio quality.
Buffering the multimedia data directly in the L1 cache system instead of main memory might be beneficial as cache memory accesses are faster and more efficient than accesses to system memory. However, directly buffering the multimedia data in the L1 cache system 15 and bypassing main memory storage may be impractical because cache memories cannot be used directly by peripheral devices to store data.
Therefore, it would be desirable to have a multimedia device capable of allowing real-time CPU processing of multimedia data while accomplishing other CPU-related tasks. Such a device would be able to effectively process and display video images and broadcast audio signals without losing the quality or usefuilness inherent to the information.